Phase-locked loops (PLLs) are used in a variety of applications, such as clock and data-recovery circuits, clock-generation circuits, and communication circuits. Implemented as frequency synthesizers, PLLs may be used to transmit and receive data in wireless communication transceivers, which may be used in wireless sensor networks, point-to-point data links, wireless local area networks (WLANs), WiMax applications, mobile phones, and data streaming applications.
The design of wireless communication transceivers may be difficult, however, due to a large number of practical and regulatory constraints. For example, wireless sensor network transceivers may operate in the industrial, scientific, and medical (ISM) band (at, e.g., 900 MHz or 2.4 GHz), which is regulated by various communication standards such as the emerging IEEE 802.15.4, SP100, and/or WirelessHART standards. Transceivers in wireless sensor networks may require ultra-low power consumption per unit (e.g., less than 25 mW in transmit mode), low selling price per unit (e.g., less than $1), and increasingly higher levels of integration of the digital-signal processing functions. Wireless sensor networks using Direct Sequence Spread Spectrum (DSSS) modulation, high-quality audio and video streaming applications, and other data-intensive applications require high rates of data transmission—for example, 2-4 Mbps. These high data rates may need a low modulation error rate (MER) or, equivalently, a low error-vector magnitude (EVM) and high signal-to-noise ratio (SNR) at the transmitter output to preserve the modulation accuracy.
Traditionally, cartesian RF modulators have been used to transmit high-data-rate signals; this type of modulator, however, depends heavily on analog circuitry. Analog circuit imperfections, such as quadrature-phase and gain mismatches, single-side band suppression, and direct LO feed-through considerably impair the modulation accuracy of cartesian-based transmitters. Cartesian RF modulators also require, in addition to a frequency synthesizer, two channels of digital-to-analog converters (DACs), low-pass filters, and RF mixers with inductive loads. These circuits are expensive both in terms of silicon area and power consumption.
An alternative approach uses a frequency-synthesizer-based transmitter to mitigate some of the drawbacks associated with cartesian RF modulators. Traditional frequency-synthesizer-based transmitters, however, suffer from an inherent trade-off between MER and spectral emissions, thereby limiting their maximum data rate. One possible solution is to extend the bandwidth of the (primarily analog) frequency-synthesizer-based transmitter using digital pre-emphasis techniques, thereby improving its MER at high data rates as well as reduce its spectral emissions. The transfer function of the analog-based frequency synthesizer, however, may vary with process tolerances and temperature variations, while the digital circuitry may have a constant, invariable transfer function. This difference in behavior may create a mismatch between the analog transfer function of the frequency synthesizer and the digital transfer function used for pre-emphasis. This mismatch may cause the cascaded (i.e., analog plus digital) bandwidth of the frequency synthesizer to significantly deviate from the target bandwidth as operating and process conditions change. It is crucial, however, to maintain the accuracy of the match between the digital and analog transfer functions to guarantee a minimal (e.g., less than ±10%) variation of the cascaded bandwidth of the frequency synthesizer transfer function.
Various schemes to calibrate the bandwidth of a frequency synthesizer exist. One such scheme is based on locking the frequency synthesizer at two different frequencies separated by a known difference (Δfcal) and measuring the difference between the loop-filter tuning voltages (ΔVcal) at each frequency. Using the value of Δfcal/ΔVcal, the gain of a voltage-controlled oscillator (VCO) may be estimated and its variation from the nominal value may be derived. This scheme uses either a high-resolution analog-to-digital converter (ADC) to directly measure the loop-filter tuning voltage or an amplifier circuit to measure ΔVcal and an ADC to digitize the measurement. The digitized output of the ADC is then used to address a look-up table (LUT) to obtain the calibrated charge-pump current of the frequency synthesizer. Increasing (or decreasing) the charge-pump current causes the bandwidth of the frequency synthesizer to increase (or decrease).
This scheme, however, has two main shortcomings. First, components other than the VCO gain variation may affect the bandwidth variation of the frequency synthesizer but are not accounted for. For example, the characteristics of the loop filter and/or the charge pump may significantly vary with process conditions and temperature, but the differences would not be calibrated. Second, a high-resolution ADC and a high-accuracy difference amplifier each consume a large amount of silicon area, thereby increasing cost, complexity, and/or power consumption.
A second scheme for closed-loop bandwidth calibration of a PLL-based frequency synthesizer calibrates the variations of all the individual contributors to the overall variation of the bandwidth. This second scheme, however, also suffers from two major drawbacks. First, it requires an additional calibration port at the VCO input during calibration. Although the additional calibration port may be also used for modulation, in the case where a pre-emphasis filter is used, extra circuitry is required for the second port. In addition, the closed-loop calibration circuitry will introduce errors once it is removed after calibration. Second, the preferred method of calibration in this scheme is through the VCO amplitude control, which controls the VCO gain. The variation in bandwidth, however, may be excessive, and absorbing a large variation in the VCO gain poses significant stability and linearity issues in the closed-loop response of the frequency synthesizer.
Given the above shortcomings of existing calibration systems, a need exists for a simple, area- and power-efficient, accurate, and comprehensive calibration system and method for PLLs and, in particular, PLL-based frequency synthesizers.